1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a circuit capable of quickly synchronizing a plurality of clocks having different frequencies, where the clocks are used in a semiconductor memory device operating at high speed.
2. Description of the Related Art
In a system including a plurality of semiconductor memory devices, the semiconductor memory devices store data. When a data processing device, for example, a memory control unit (MCU) or the like requests data, a semiconductor memory device outputs data corresponding to an address inputted from the data requesting device or stores data provided from the data requesting device in a position corresponding to the address.
For such an operation, semiconductor memory devices operating at high speed, which have been recently developed, are designed in such a manner as to input/output two bits of data between rising and falling edges of a system clock applied from outside and input/output two bits of data between the falling edge and the next rising edge. Thus, the semiconductor memory devices are designed in such a manner as to input/output four bits of data during one cycle of the system clock.
However, since the system clock is represented, for example, only by two states, i.e., a logic high level and a logic low level, a data clock having a frequency two times higher than the system clock is used to input/output four bits of data during one cycle. That is, a data clock dedicated to data input/output is used.
Therefore, a semiconductor memory device operating at high speed controls the data clock to have a frequency two times higher than the system clock, using the system clock as a reference clock when transmitting/receiving an address and a command and using the data clock as the reference clock when inputting/outputting data.
That is, the semiconductor memory device controls two cycles of the data clock to be repeated during one cycle of the system clock, and controls data input/output to occur at rising and falling edges of the data clock such that four bits of data may be inputted/outputted during one cycle of the system clock.
Unlike a conventional DDR synchronous memory device using one system clock as a reference clock to perform a read or write operation, the semiconductor memory device operating at high speed transmits and receives data using two clocks having different frequencies, in order to perform a read or write operation.
However, when the phases of the system clock and the data clock are not aligned with each other, the phase of the reference clock for transmitting an operation command and an address is not aligned with the phase of the reference clock for transmitting data. In this case, the semiconductor memory device operating at high speed may not operate normally.
Therefore, to normally operate the semiconductor memory device operating at high speed, interface training is to be performed between the semiconductor memory device and the data processing device at the initial stage of the operation.
Here, the interface training indicates that an interface for transmitting a command, an address, and data is trained so as to operate with an optimized timing, before a normal operation between the semiconductor memory device and the data processing device is performed.
The interface training may be divided into address training, clock alignment training (WCK2CK training), read training, write training and so on. Among them, an operation of aligning a data clock and a system clock is performed during the clock alignment training (WCK2CK training).
Meanwhile, when the semiconductor memory device is in a self refresh mode, a system clock and a data clock are not applied from outside, and a system clock buffer and a data clock buffer are disabled and initialized to save electricity. In this case, clock alignment training information disappears. Therefore, in accordance with the conventional semiconductor memory device, when exiting from the self refresh mode, the semiconductor memory device performs a clock alignment training mode or automatic synchronization mode and compares the phases of the system clock and the data clock to perform a normal operation. At this time, the clock alignment training mode or the automatic synchronization mode is performed by a command signal from outside. For example, the command signal from outside may be applied at a predetermined time after the semiconductor memory device exits from the self refresh mode. Therefore, during the clock alignment training mode, a normal operation is not performed and affects the performance of the semiconductor memory device.